Tuesday, October 23, 2012

Timing based Interview Questions

Interview Questions

Usually there are 2 phase of interview- 
  1. Over the phone (Phone Screen) and 
  2. Face to Face.
Candidates have a wrong myth about the fact that interview over the phone is very easy and what interviewer can ask in that. When this year I have to recruit for my team then I has done a lot of phone screening and I have figured out that candidate usually take it very lightly. They don’t think the importance of the phone screening. 

Phone Screen Questions:

First we will discuss all those questions which can be the part of Phone screening. These can vary as per the Job profile and requirement but still more and less these are standard.
These are the questions which are not in much details but it will give the insight of your expertise and experience to the interviewer, which help him/them to further screening the profile.  
I will discuss the questions in several areas one by one.

Let’s start in the area of timing. Remember- I am also listing the Expected Ans in one word or one sentence. But expect the WHY/HOW as part of follow-on question. I have mentioned few follow-on questions also (without Ans). For the detailed ans of any topic, please read the different articles in the ( VLSI CONCEPTS ) http://vlsi-expert.com or refer any other book/weblink.
You Can also refer following book for more similar type of questions.
VLSI INTERVIEW QUESTION: Static Timing analysis : Puneet Mittal (Author)

Above Book is a Kindle edition. For that you have to download a "Free Kindle App" on you mobile/desktop/tablets. You can download Kindle App using following link.Amazon.com - Read eBooks using the FREE Kindle Reading App on Most Devices

Timing Related

  • Q: In which tool you have experience related to timing/STA?  
  • Expected answer (any): Synopsys Primetime, Magma Tekton, (etc  ...)
  • Follow-On questions :
    • Which one is industry standard?
    • Which one is more accurate?
    • On which version, you have worked?
    • Any major difference in the 2 versions? (this question is going to ask if it’s the demand of job profile)
    • How are you qualifying particular STA tool?
    • Any 2 good STA tool with preferance. Also tell 1 good and 1 bad thing in both the tools.
  • Q: In which part of the design we do the STA run.
  • Expected answer: Any part we can do. But mostly once before the layout (after the synthesis) and then 2-3 times post layout. Signoff we usually do after the routing.
  • Follow-On questions:
    • On which side you have used?
    • What’s the difference in terms of Input and accuracy in pre-layout and post-layout STA?
    • Which one is more accurate and which one is fast?
    • Why we want to do it twice or trice?
    • Reference Article: Basic Of Timing Analysis ; First para of STA ; STA using EDA tool part2
  • Q:  What are the input files required to run STA?
  • Expected answer:  Gate level netlist, Parasitics file(SPEF/SBPF), Constraints (SDC or tcl), general setup scripts.
  • Follow-On questions:
    • What’s the source of these files? (means which one is coming from foundry/EDA vendor/internal)
    • What’s the information present in these files which helps for delay calculation?
    • What will happen in the absence of any/few of these files?
    • In the absence of SPEF, which other data can be used?
      • Expected answer: SDF, SBPF, DSPF, SPF. (But basically the intent of question is that if you don’t have any parasitic info in any available format, then SDF is the best solution).
    • What if we don’t have the SDF also?
      • Expected answer: Wire load model
    • Which one is accurate and which one is fast to read in a STA tool out of SDF or SPEF?
      • Expected answer: SDF is fast to read but SPEF is more accurate.
  • Q: What is the main objective of timing closure in STA?
  • Expected answer (any): Run necessary PVT/RC corners and close any negative slack path (hold slack/setup slack), Fixing any Timing DRC Error. Some time we have positive slack but because of constraint or say margin we have to set a margin value (like 5ps), so any path which has less then 5ps slack also has to fix. Same scenerio happen for negative case also. 

  • Q:  What’s the different between Crosstalk and without crosstalk based STA analysis.
  • Expected answer: In the cross talk based analysis, we want to see the impact of coupling capacitance and Noise on our circuit In addition to normal STA analysis. Without Crosstalk based analysis, we want to do normal delay analysis on the basis of skew/load/driving strength/clock pulse/frequency etc.
  • Follow-On questions:
    • Which files are necessary for crosstalk based STA run?
    • Expected answer: Specially Interconnect parasitic file with coupling information.
    • What will happen if we will not do the cross-talk based analysis?
    • What should be the sequence of analysis?
    • From which technology node onward, crosstalk based analysis become critical? And Why 
  • Q: Why should crosstalk be avoided?
  • Expected answer: Crosstalk causes signals to be delayed and can cause noise glitch on signals resulting in improper function.

  • Q: Why are we using the timing constraints?
  • Expected answer: The timing constraints define the operating environment the design/chip on which the final product should work such as clocks, clock frequency, margins. These constraint are defined in the .Libs files also and in the SDC also. 
  • Follow-On questions:
    • There are few constraints also present in the .lib files, then how SDC is different from that?
    • Can I over write the constraint defined in the .lib files in my design?
    • Pick any one constraint and explain the significance of that in the design.
    • Reference Article : SDC
  • Q: In the Hierarchical design, there are different Blocks. How are we capturing the timing information of those blocks in our design?
  • Expected answer: Using the timing models of those blocks. Like ETM/QTM/ILM/dbs
  • Follow-On questions:
    • What’s the basic difference in the ETM and ILM models?
    • What types of information are present in the ETM and ILM?
    • Out of ETM and ILM, which one is more accurate?
    • Which one you have used in your design?
    • How are you generating that model?
    • How accurate are those in terms of full-flat design?
    • Reference Article : ETM Basics part1 ; Hierarchical Design part1 ; Hierarchical Design part2

  • Q: What’s the main difference between OCV and AOCV.
  • Expected Ans (or similar answer): On-Chip-Variation (OCV) timing analysis uses a constant derating factor; whereas AOCV applies derated value is a function of path-depth and possibly distance.

  • Q: What’s the difference between PVT corner and RC corners?
  • Expected Answer (or similar answer): PVT corners represent transistor Process (Slow /Fast) corner, and Voltage and Temperature operating conditions. RC corners are related to the metal (back-end) fabrication process. Width/thickness of wire can change by small amount during the fabrication. It will impact resistance and capacitance. So there are different interconnect RC corners.
  • Follow-On Questions:
    • How many PVT corners are there in 28nm/40nm technology node? Or (the node on which you are working/worked)
    • What’s the difference between Slow and Fast corner?
    • Why we need different corner for different temperature and voltage?
    • Who is deciding these corners? (foundry/vendor/your company)

 In the next part, we will discuss More about the timing interview questions.

Recommended Book:
VLSI INTERVIEW QUESTION: Static Timing analysis : Puneet Mittal (Author)


  1. where can i find the next part??

    1. In place of writing a series of 27Post I have composed all those in a book. You can find the link of the book above.
      I hope that will help you.

  2. It's all about timing when it comes to best performing Chip design !!


    Happy Learning !!
    Kunal Ghosh


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