Saturday, July 12, 2008

Spice model Based Vlsi Interview Questions

I am listing few question asked by someone to me...

  1. What do you means by Parasitic rule generation?
  2. What are the different informations contain a spice model?
  3. What are the different variation rules?
  4. What is CMP effect? Why foundry define these rules?
  5. What is IMD variation rules?Why foundry define these rules?
  6. What is Trap rules?Why foundry define these rules?
  7. What is Density variation rules in the RC rules? Why foundry define these rules?
  8. Why there is need of RC rules?
  9. Why we define resistance rules for metals and Vias?
  10. if the thickness of metal increases , resistance increases or decreases?
  11. What is etch rules?Why foundry define these rules?
  12. What data is given in the spice model for generation of etch rules and how you calculate the etch value from that data?
  13. What are thickness variation rules? how it effects the capacitance?
  14. What is OPC rules?Why foundry define these rules?
  15. What are the different types of Cap rules?
  16. What do mean by best case, worst case, typical case?
  17. What do you mean by 2D and 3D extraction of capacitance?
  18. What is SPEF?
  19. What is the role dielectric between two metal layers?
  20. Why temperature coefficients are defined in the RC rules?
  21. How we extract the capacitance from a real design?
  22. What is the significance of floating metals and how it effects the capacitance?
  23. What are the different constraint faced by the foundry during defining the rules?
  24. if we consider an ideal case (means no CMP effect, no thickness variation , no width variation ), how it effects the rules?
  25. Why now a days we use copper (Cu) and not Al for metal layers.

2 comments:

  1. This comment has been removed by the author.

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  2. It would be great full if answers are also provided

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